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19-1571; Rev 0; 12/99
Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC
General Description
The MAX5544 serial-input, voltage-output, 14-bit monotonic digital-to-analog converter (DAC) operates from a single +5V supply. The DAC output is unbuffered, resulting in low 0.3mA supply current and low 1LSB offset error. The DAC output range is 0V to VREF. The DAC latch accepts a 16-bit serial word. A power-on reset circuit clears the DAC output to 0V (unipolar mode) when power is initially applied. The 10MHz 3-wire serial interface is SPITM/QSPITM/ MICROWIRETM compatible and interfaces directly with optocouplers for applications requiring isolation. The MAX5544 is available in an 8-pin SO package. o +5V Single-Supply Operation o Low Power: 1.5mW o 1s Settling Time o Unbuffered Voltage Output Directly Drives 60k Loads o SPI/QSPI/MICROWIRE-Compatible Serial Interface o Power-On Reset Circuit Clears DAC Output to 0V (unipolar mode) o Schmitt Trigger Inputs for Direct Optocoupler Interface
Features
o Full 14-Bit Performance Without Adjustments
MAX5544
Applications
High-Resolution Offset and Gain Adjustment Industrial Process Control Automated Test Equipment Data Acquisition Systems
PART MAX5544CSA MAX5544ESA
Ordering Information
TEMP. RANGE 0C to +70C -40C to +85C PIN-PACKAGE 8 SO 8 SO
Pin Configuration
TOP VIEW
Functional Diagram
VDD
MAX5544
REF OUT 1 AGND 2 REF 3 CS 4 8 VDD 14-BIT DAC OUT AGND CS DIN SCLK 16-BIT DATA LATCH CONTROL LOGIC SERIAL INPUT REGISTER
MAX5544
7 DGND 6 DIN 5 SCLK
SO
DGND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC MAX5544
ABSOLUTE MAXIMUM RATINGS
VDD to DGND............................................................-0.3V to +6V CS, SCLK, DIN to DGND..........................................-0.3V to +6V REF to AGND...............................................-0.3V to (VDD +0.3V) AGND to DGND.....................................................-0.3V to +0.3V OUT to AGND, DGND.................................. ............-0.3V to VDD Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.88mW/C above +70C)................471mW Operating Temperature Ranges MAX5544CSA .....................................................0C to +70C MAX5544ESA ..................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 5%, VREF = +2.5V, VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Resolution Differential Nonlinearity Integral Nonlinearity Zero-Code Offset Error Zero-Code Tempco Gain Error (Note 1) Gain-Error Tempco DAC Output Resistance Power-Supply Rejection REFERENCE INPUT Reference Input Range Reference Input Resistance (Note 4) Voltage-Output Slew Rate Output Settling Time VREF RREF (Note 3) 2.0 11.5 3.0 V k ROUT PSR (Note 2) 4.75V VDD 5.25V SYMBOL N DNL INL ZSE ZSTC Guaranteed monotonic VDD = 5V TA = +25C TA = TMIN to TMAX TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 0.1 6.25 1.0 0.05 5 10 CONDITIONS MIN 14 0.5 4 1.0 8 1 2 TYP MAX UNITS Bits LSB LSB LSB ppm/C LSB ppm/C k LSB STATIC PERFORMANCE--ANALOG SECTION (RL = )
DYNAMIC PERFORMANCE--ANALOG SECTION (RL = ) SR CL = 10pF (Note 5) To /2LSB of FS, CL = 10pF
1
25 1
V/s s
2
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC MAX5544
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%, VREF = +2.5V, VAGND = VDGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC Glitch Impulse Digital Feedthrough Major-carry transition Code = 0000 hex, CS = VDD, SCLK = VDIN = 0 to VDD levels BW SNR CIN Code = 0000 hex Code = FFFC hex 2.4 0.8 VIN = 0 (Note 6) 0.40 4.75 0.3 1.5 5.25 1.1 1 10 Code = FFFC hex Code = 0000 hex, VREF = 1Vp-p at 100kHz 10 10 nVs nVs
DYNAMIC PERFORMANCE--REFERENCE SECTION Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance 1 1 83 75 120 MHz mVp-p dB pF
STATIC PERFORMANCE--DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance Hysteresis Voltage POWER SUPPLY Positive Supply Range Positive Supply Current Power Dissipation VDD IDD PD V mA mW VIH VIL IIN CIN VH V V A pF V
TIMING CHARACTERISTICS
(VDD = +5V 5%, VREF = +2.5V, VAGND = VDGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold SCLK High to CS High Hold DIN to SCLK High Setup DIN to SCLK High Hold VDD High to CS Low (power-up delay) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: SYMBOL fCLK tCH tCL tCSS0 tCSS1 tCSH0 tCSH1 tDS tDH (Note 6) 45 45 45 45 30 45 40 0 20 CONDITIONS MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns s
Gain error tested at VREF = +2.0V, +2.5V, and +3.0V. ROUT tolerance is typically 20%. Min/max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance. Reference input resistance is code dependent, minimum at 8554 hex. Slew-rate value is measured from 0% to 63%. Guaranteed by design. Not production tested.
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC MAX5544
Typical Operating Characteristics
(VDD = +5V, VREF = +2.5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX5544-01
SUPPLY CURRENT vs. REFERENCE VOLTAGE
0.34 0.33 SUPPLY CURRENT (mA) 0.32 0.31 0.30 0.29 0.28 0.27 0.26
MAX5544-02
ZERO-CODE OFFSET ERROR vs. TEMPERATURE
0.15 ZERO-CODE OFFSET ERROR (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
MAX5544-03
0.50 0.45 SUPPLY CURRENT (mA) 0.40 0.35 0.30 0.25 0.20 -40 -20 0 20 40 60 80
0.35
0.20
0.25 100 0 1 2 3 4 5 6 TEMPERATURE (C) REFERENCE VOLTAGE (V)
-60
-20
20
60
100
140
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5544-04
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX5544-05
GAIN ERROR vs. TEMPERATURE
0.15 0.10
MAX5544-06
0.30 0.20 0.10 INL (LSB) 0 -0.10 -0.20 -0.30 -60 -20 20 60 100 -INL
0.30 0.20
0.20
+INL DNL (LSB)
+DNL
GAIN ERROR (LSB) 140
0.10 0
0.05 0 -0.05 -0.10
-DNL -0.10 -0.20 -0.30
-0.15 -0.20 -60 -20 20 60 100 -60 -20 20 60 100 140 TEMPERATURE (C) TEMPERATURE (C)
140
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. CODE
MAX5544-07
DIFFERENTIAL NONLINEARITY vs. CODE
MAX5544-08
REFERENCE CURRENT vs. CODE
MAX5544-09
0.250
0.250
200
REFERENCE CURRENT (A)
0.125 INL (LSB)
0.125
160
0
DNL (LSB)
120
0
80
-0.125
-0.125
40
-0.250 0 5k 10k DAC CODE 15k 20k
-0.250 0 5k 10k DAC CODE 15k 20k
0 0 4k 8k 12k 16k 20k DAC CODE
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC
Typical Operating Characteristics (continued)
(VDD = +5V, VREF = +2.5V, TA = +25C, unless otherwise noted.)
FULL-SCALE STEP RESPONSE (fSCLK = 10MHz)
MAX5544-10
MAX5544
FULL-SCALE STEP RESPONSE (fSCLK = 20MHz)
MAX5544-11
OUT 500mV/div
OUT 500mV/div
1s/div CL = 13pF RL = CL = 13pF RL =
400ns/div
MAJOR-CARRY OUTPUT GLITCH
MAX5544-12
DIGITAL FEEDTHROUGH
MAX5544-13
CS 5V/div
SCLK 5V/div
OUT AC-COUPLED 100mV/div 2s/div 2s/div
OUT AC-COUPLED 50mV/div
CODE = 0000 hex
______________________________________________________________Pin Description
PIN 1 2 3 4 5 6 7 8 NAME OUT AGND REF CS SCLK DIN DGND VDD DAC Output Voltage Analog Ground Voltage Reference Input. Connect to external +2.5V reference. Chip-Select Input Serial-Clock Input. Duty cycle must be between 40% and 60%. Serial-Data Input Digital Ground +5V Supply Voltage FUNCTION
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC MAX5544
Detailed Description
The MAX5544 voltage-output, 14-bit digital-to-analog converter (DAC) offers 14-bit monotonicity with less than 1LSB differential linearity error. Serial-data transfer minimizes the number of package pins required. The MAX5544 is composed of two matched DAC sections, with a 12-bit inverted R-2R DAC forming the 12LSBs and the 4MSBs derived from 15 identically matched resistors. This architecture allows the lowest glitch energy to be transferred to the DAC output on major-carry transitions. It also decreases the DAC output impedance by a factor of eight compared to a standard R-2R ladder, allowing unbuffered operation in medium-load applications. Figure 1 is the timing diagram. synchronously and latched into the input register on the rising edge of the serial-clock input (SCLK). After 16 data bits (14 data bits, plus two sub-bits set to zero) have been loaded into the serial input register, it transfers its contents to the DAC latch on CS's low-to-high transition (Figure 2). Note that if CS does not remain low during the entire 16 SCLK cycles, data will be corrupted. In this case, reload the DAC latch with a new 16-bit word.
External Reference
The MAX5544 operates with external voltage references from 2V to 3V. The reference voltage determines the DAC's full-scale output voltage.
Power-On Reset
The MAX5544 has a power-on reset circuit to set the DAC's output to 0V in unipolar mode when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system power-up, such as after power loss. In bipolar mode, the DAC output is set to -VREF.
Digital Interface
The MAX5544 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE interfaces. The chip-select input (CS) frames the serial data loading at the data input pin (DIN). Immediately following CS's high-to-low transition, the data is shifted
;;;;;;;; ;;;;;;;;; ; ; ;;
tCSH1 CS tCSHO tCSSO tCH tCL tCSS1 SCLK tDH tDS DIN D13 D12 S0
Figure 1. Timing Diagram
CS
DAC UPDATED
SCLK
SUB-BITS
DIN
D13 D12 D11 D10 D9 D8 D7 D6 MSB
D5 D4 D3 D2 D1 D0 S1 S0 LSB
Figure 2. 3-Wire Interface Timing Diagram
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC MAX5544
Applications Information
Reference and Analog Ground Inputs
The MAX5544 operates with external voltage references from 2V to 3V, and maintains 14-bit performance with proper reference selection and application. Ideally, the reference's temperature coefficient should be less than 1.5ppm/C to maintain 14-bit accuracy to within 1LSB over the commercial (0C to +70C) temperature range. Since this converter is designed as an inverted R-2R voltage-mode DAC, the input resistance seen by the voltage reference is code dependent. The worstcase input-resistance variation is from 11.5k (at code 8555 hex) to 200k (at code 0000 hex). The maximum change in load current for a 2.5V reference is 2.5V / 11.5k = 217A; therefore, the required load regulation is 28ppm/mA for a maximum error of 0.1LSB. This implies a reference output impedance of <71m. In addition, the impedance of the signal path from the voltage reference to the reference input must be kept low because it contributes directly to the load-regulation error. The requirement for a low-impedance voltage reference is met with capacitor bypassing at the reference inputs and ground. A 0.1F ceramic capacitor with short leads between REF and AGND provides high-frequency bypassing. A surface-mount ceramic chip capacitor is preferred because it has the lowest inductance. An additional 10F between REF and AGND provides lowfrequency bypassing. A low-ESR tantalum, film, or organic semiconductor capacitor works well. Leaded capacitors are acceptable because impedance is not as critical at lower frequencies. The circuit can benefit from even larger bypassing capacitors, depending on the stability of the external reference with capacitive loading. If separate force and sense lines are not used, connect the appropriate force and sense pins together close to the package. AGND must also be low impedance, as load-regulation errors will be introduced by excessive AGND resistance. As in all high-resolution, high-accuracy applications, separate analog and digital ground planes yield the best results. Connect DGND to AGND at the AGND pin to form the "star" ground for the DAC system. For the best possible performance, always refer remote DAC loads to this system ground. impedance is also low enough to drive medium loads (RL > 60k) without degradation of INL or DNL; only the gain error is increased by externally loading the DAC output.
External Output Buffer Amplifier
In unipolar mode, the output amplifier is used in a voltage-follower connection. The DAC's output resistance is constant and is independent of input code; however, the output amplifier's input impedance should still be as high as possible to minimize gain errors. The DAC's output capacitance is also independent of input code, thus simplifying stability requirements on the external amplifier. In single-supply applications, precision amplifiers with input common-mode ranges including AGND are available; however, their output swings do not normally include the negative rail (AGND) without significant performance degradation. A single-supply op amp, such as the MAX495, is suitable if the application does not use codes near zero. Since the LSBs for a 14-bit DAC are extremely small (152.6V for VREF = 2.5V), pay close attention to the external amplifier's input specification. The input offset voltage can degrade the zero-scale error and might require an output offset trim to maintain full accuracy if the offset voltage is greater than 1/2LSB. Similarly, the input bias current multiplied by the DAC output resistance (typically 6.25k) contributes to the zero-scale error. Temperature effects also must be taken into consideration. Over the commercial temperature range, the offset voltage temperature coefficient (referenced to +25C) must be less than 1.7V/C to add less than 1/2LSB of zero-scale error. The external amplifier's input resistance forms a resistive divider with the DAC output resistance, which results in a gain error. To contribute less than 1/2LSB of gain error, the input resistance typically must be greater than: 6.25k / 1 1 = 205M 2 214
Unbuffered Operation
Unbuffered operation reduces power consumption as well as offset error contributed by the external output buffer. The R-2R DAC output is available directly at OUT, allowing 14-bit performance from +VREF to AGND without degradation at zero-scale. The DAC's output
The settling time is affected by the buffer input capacitance, the DAC's output capacitance, and PC board capacitance. The typical DAC output voltage settling time is 1s for a full-scale step. Settling time can be significantly less for smaller step changes. Assuming a single time-constant exponential settling response, a full-scale step takes 10.4 time constants to settle to within 1/2LSB of the final output voltage. The time constant is equal to the DAC output resistance multiplied by the total output capacitance. The DAC output capacitance is typically 10pF. Any additional output capacitance will increase the settling time.
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Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC
The external buffer amplifier's gain-bandwidth product is important because it increases the settling time by adding another time constant to the output response. The effective time constant of two cascaded systems, each with a single time-constant response, is approximately the root square sum of the two time constants. The DAC output's time constant is 1s / 10.4 = 96ns, ignoring the effect of additional capacitance. If the time constant of an external amplifier with 1MHz bandwidth is 1 / 2 (1MHz) = 159ns, then the effective time constant of the combined system is: 2 2 96ns + 159ns = 186ns
MAX5544
Table 1. Unipolar Code Table
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 11(00) 1000 0000 0000 00(00) 0000 0000 0000 01(00) 0000 0000 0000 00(00) ANALOG OUTPUT, VOUT VREF * (16,383 / 16,384) VREF * (8192 / 16,384) = 1/2VREF VREF * (1 / 16,834) 0V
Power-Supply Bypassing and Ground Management
For optimum system performance, use PC boards with separate analog and digital ground planes. Wire-wrap boards are not recommended. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND together at the IC. The best ground connection can be achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass VDD with a 0.1F ceramic capacitor connected between V DD and AGND. Mount it with short leads close to the device. Ferrite beads can also be used to further isolate the analog and digital power supplies.
( )(
)
This suggests that the settling time to within 1/2LSB of the final output voltage, including the external buffer amplifier, will be approximately 10.4 * 186ns = 1.93s.
Digital Inputs and Interface Logic
The digital interface for the 14-bit DAC is based on a 3wire standard that is SPI/QSPI/MICROWIRE compatible. The three digital inputs (CS, DIN, and SCLK) load the digital input data serially into the DAC. All of the digital inputs include Schmitt-trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5544 without additional external logic. The digital inputs are TTL/ CMOS-logic compatible.
Chip Information
TRANSISTOR COUNT: 2209 SUBSTRATE CONNECTED TO DGND
Unipolar Configuration
Figure 3 shows the MAX5544 configured for unipolar operation with an external op amp. The op amp is set for unity gain, and Table 1 shows the codes for this circuit.
+2.5V +5V 0.1F 0.1F 10F
MC68XXXX
PCS0 MOSI SCLK CS DIN SCLK
VDD
REF UNIPOLAR OUT
MAX495 MAX5544
OUT EXTERNAL OP AMP
DGND
AGND
Figure 3. Typical Operating Circuit
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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